The Integrated Circuit (IC) design process typically involves specifying the functionality of the chip in a standard hardware programming language such as verilog; synthesizing/mapping the circuit description into basic gates of a Standard Cell Library using Computer Aided Design (CAD) tools such as Synopsys' DesignCompiler; placing and routing the gate netlist using CAD tools, and finally verifying proper connectivity and functionality of the circuit.
While all of these steps are very important in determining the quality of the Integrated Circuit, for most of these steps, the achievable quality of implementation is design dependent. However, the Standard Cell Library can make all IC designs better, i.e., the quality of the Standard Cell Library influences all designs, and as such it has a far reaching influence on the quality of chips. The standard cell library provides the ingredients of a chip and thus limits the achievable quality of the final product.
Many library development efforts have focused on high speed designs. However, library improvement opportunities on the lower frequency end of the spectrum (e.g., Bluetooth or Gigabit PHY products) exist as well. In the past, technology scaling had provided the necessary speed increases. With the advent of technology scaling, higher and higher levels of integration became possible due to the shrinking device sizes. Technology scaling was providing not only an area scaling but also a delay scaling. According to Moore's “Law”, chips were doubling their speed every 18 months. While this “law” has been applicable for more than 20 years, a point has been reached where process scaling no longer delivers the expected speed increases. This is mainly due to the fact certain device parameters have reached atomic scales. One of the consequences of this speed saturation due to technology scaling is that designers must work harder at each stage of the design flow to achieve the last remaining circuit performance. Even small speed increases will come at significantly higher design efforts than in the past. Therefore having the best standard cell library is critical.
One technique being considered to achieve higher library speeds is the implementation of a 14-track standard cell library. This library has a cell height 40% larger than that of the base line standard cell library that is 10-tracks. The extra height allows for more active area (transistors) to be packed into cells and thus makes for more speed-efficient building blocks. However, the speed increase comes with a cost of added area and power which many portable applications are not able to tolerate. The added area increases fabrication costs, while the added power consumption (both dynamic and leakage power) reduces the battery life of products using the resulting chips.
What is therefore needed are design tools, such as enhanced Standard Cell Libraries, that can produce circuits having optimal speed and area.
What is further needed is an enhanced standard cell library that allows smooth intermixing of any track height cells and provides an effective way to combine the area/power efficiency of “short” cells with the speed advantage of “tall” cells.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.